Danish Kapoor
Danish Kapoor

TSMC and Samsung have a problem: the per-wafer yield of their best lithography leaves a lot to be desired

3nm lithography is still uncomfortable for the two chipmakers that have started large-scale production with it. Samsung began manufacturing GAAFET ICs with this integration technology in June 2022, and TSMC began large-scale production in Taiwan of 3nm chips in December 2022. For these two companies, the launch of these lithography nodes It was a very important milestone., but we have tangible reasons to accept that their plan has not turned out as they had anticipated. At least not at all.

When semiconductor manufacturers produce a chip wafer, some of those cores do not function properly. Its normal. When a new lithographic node is launched, its performance per wafer usually has a large margin for improvement, but little by little, as engineers refine their integration processes, this parameter improves. A mature lithography can deliver very high performance to IC manufacturers, but a nascent technology can move in the orbit of 50% performance.

The outlook does not look good for TSMC or Samsung. And for Intel, neither

GAAFET technology is giving Samsung more joy than FinFET is giving TSMC. At least if we stick to 3nm lithography. This is what is defended by the report published by the South Korean financial group Hi Investment & Securities in mid-July. According to this source at that time the performance of Samsung’s 3nm node oscillated in the orbit of 60%, while the comparable TSMC node moved around 55%. At first glance it may seem like a small difference, but it is not. It is important.

Samsung and TSMC are having trouble pushing the performance of their 3nm nodes beyond 60%

In any case, both figures can clearly be improved. The fact that just over half of its 3nm chips work correctly is a problem. However, this is not the only information we have about the performance of the most advanced lithography of these IC manufacturers. At the beginning of August, several media revealed that TSMC technicians had already managed to improve their 3 nm lithographic process, so that at that time the performance of this node was around 70%. It is a significant improvement, but it is still far from being an ideal figure.

However, in a new turn of events, some South Korean media, such as Chosen Biz, claim that Samsung and TSMC’s problems with 3nm lithography persist, which is why both companies are having difficulties in bringing the performance of this node beyond 60%. The curious thing is that they need it to be at least 70% to ensure their profitability and attract more customers, which invites us to ask ourselves a question: who assumes the expenses that come with the need to throw away so many 3 nm chips? useless?

Under normal conditions, this extra cost is assumed by Samsung and TSMC customers. However, the latter company’s best client, Apple, has some privileges as a result of his position. In 2022, 23% of TSMC’s income came from the apple firm, which has allowed Tim Cook and his acolytes to force this Taiwanese manufacturer to assume the cost of the cores of each 3 nm wafer that they don’t work properly.

In this article we have not yet talked about the third company in contention: Intel. It is currently manufacturing large-scale ‘Meteor Lake’ processors with its Intel 4 EUV (extreme ultraviolet) lithography, and plans to have its Intel 3 node ready before the end of this year. We still don’t know precisely what performance this company has achieved in its cutting-edge nodes, but it’s reasonable to assume given Intel’s relative inexperience with EUV lithography that, like TSMC and Samsung, it won’t be a cakewalk for making integrated circuits either. so advanced.

Cover image: TSMC

More information: Chosen Biz

Danish Kapoor